Presently, electronic equipment are essential for many modern applications. Therefore, consumers are increasingly demanding more processing power, lower electrical power usage and cheaper devices. As the electronic industry strives to meet these demands and more complicated and denser configurations, miniaturization will result in an extension of the number of chips per wafer and the number of transistors per chip, as well as a reduction in power usage. Wafer level packaging (WLP) technology has been gaining popularity since the electronic components are being designed to be lighter, smaller, more multifunctional, more powerful, more reliable and less expensive. The WLP technology combines dies having different functionalities at a wafer level, and is widely applied in order to meet continuous demands toward the miniaturization and higher functions of the electronic components.
Stacking multiple layers of different materials on a substrate in WLP technology raises concerns about different coefficients of thermal expansion (CTE) among those layers. In contrast to a traditional packaging technology, the WLP technology is crafted on a greater scale and in a more complicated working environment. Some factors may lead to warpage of WLP as a whole, such as the differences in CTE among the stacking multiple layers. Since the CTE mismatch in the WLP technology is poorly controlled, improvements in the method for a WLP continue to be sought.